In a semiconductor manufacturing process, a plasma processing apparatus configured to perform a plasma process for the thin film deposition, the etching, or the like is widely utilized. Examples of such a plasma processing apparatus include a plasma CVD (Chemical Vapor Deposition) apparatus configured to perform a thin film deposition process, a plasma etching apparatus configured to perform an etching process, and so forth.
The plasma processing apparatus includes a processing vessel having a plasma processing space formed therein; a lower electrode provided within the processing vessel and configured to mount thereon a processing target substrate; an upper electrode disposed to face the lower electrode with the plasma processing space therebetween; and so forth. Further, the lower electrode of the plasma processing apparatus includes a conductive base member to which a high frequency power is applied; an electrostatic chuck having an insulating layer which is formed on a top surface of the base member and covers the electrode, and configured to electrostatically attract and hold the processing target substrate onto the insulating layer; a focus ring provided on a top surface of the insulating layer of the electrostatic chuck to surround the processing target substrate; and so forth.
Here, in the lower electrode of the plasma processing apparatus, a relatively large potential difference is generated between the focus ring and the processing target substrate and the base member of the lower electrode. Due to this potential difference, an electric discharge (arcing) may occur between the processing target substrate and the base member of the lower electrode or ambient structures thereof. If the electric discharge occurs between the processing target substrate and the base member of the lower electrode or the ambient structures thereof, the processing target substrate or chips on the processing target substrate may be damaged. In this regard, Patent Document 1 describes a configuration in which a resistor pin made of titania is embedded in the insulating layer of the electrostatic chuck, and the focus ring and the base member of the lower electrode are electrically connected via the resistor pin in order to reduce the potential difference between the focus ring and the base member of the lower electrode.
In the prior art technique of burying the resistor pin made of the titania in the insulating layer of the electrostatic chuck, however, impedance may be locally biased between the insulating layer of the electrostatic chuck and the resistor pin, though occurrence of the electric discharge is suppressed. Accordingly, it is difficult to maintain uniformity of a processing target surface of the processing target substrate.
Conventionally, as a way to solve this problem, there is known a method of forming a thermally sprayed film, which is conductive, on an insulating layer of an electrostatic chuck in order to suppress an electric discharge without using a resistor pin. For example, it is described in Patent Document 2 that a thermally sprayed film made of a composite material containing a mixture of an insulating material and titania is formed on the entire surface of the insulating layer of the electrostatic chuck, and a processing target substrate is attracted to and held on this thermally sprayed film. In this configuration, since the processing target substrate and the base member of the lower electrode are electrically connected via the thermally sprayed film containing the titania, an electric potential difference between the processing target substrate and the base member of the lower electrode can be reduced, and, resultantly, an electric discharge can be suppressed.
Patent Document 1: Japanese Patent Laid-open Publication No. 2011-210958
Patent Document 2: Japanese Patent Laid-open Publication No. H09-069554